1. Technical Field
The present invention relates to a variable delay circuit, a test apparatus, and an electronic device. In particular, the present invention relates to a variable delay circuit that outputs an output signal delayed with respect to an input signal by a designated time period, and to a test apparatus and an electronic device equipped with such a variable delay circuit.
2. Related Art
A conventional test apparatus includes a variable delay circuit that outputs a timing signal delayed with respect to a reference clock by a designated time period. For example, WO 2005/060098 discloses a variable delay circuit that changes the delay time by controlling the power supply current of the delay element by a MOS transistor for example.
It is desirable that the variable delay circuit disclosed in WO 2005/060098 causes the MOS transistor in a saturated region to control the power supply current of the delay element. Accordingly, the variable delay circuit is able to cause the MOS transistor to operate as a power current supply, to improve the linearity of the delay time.
In recent years, however, the power supply voltage of a CMOS circuit has decreased, making it difficult to realize a large Vds for a MOS transistor of a variable delay circuit. In addition, if the Vgs of the MOS transistor cannot be made large, the variable delay circuit cannot run a large power current to the delay element. When using a small Vds to run a large power current to the delay element, the variable delay circuit cannot easily operate the MOS transistor in a saturated region, which degrades the linearity of the delay time.